In an electronic device which outputs multi-bit data in parallel, the noise generated at the time of data transition poses a problem. This noise is produced most severely at the time of a transition corresponding to the switching of a CMOS logic circuit and the large amount of power is dissipated at the time of the transition. As a technique for reducing the number of transition times of the output data signals at the time of switching in a logic circuit, there is known a function of data inversion. This data inversion is of such a function in which data of a given cycle is compared to data output in a directly previous cycle and, in case the major part of the totality of N bits constituting the data, for example, N/2 bits or more, are switched, the logic of the data of the given cycle is inverted to output the resulting data, such as to reduce the number of bits of data actually switched on an external bus to N/2 bits or less, thereby reducing the noise or current consumption.
FIG. 8 depicts a representative configuration of a conventional data inversion circuit. The data inversion circuit shown in FIG. 8 is assumed to be employed, for example, in a clock synchronized semiconductor memory device equipped with a burst read operation. The data inversion circuit comprises a data comparator circuit 210, a majority decision circuit-data inversion flag generating circuit 310, a data inverting circuit 510 and a previous data holding circuit 810. Referring to FIG. 8, the operation of the data inversion circuit will be described step by step in the below.    1. The data comparator circuit 210 compares data 110 on the data bus to data 820 of the previous cycle, output from the previous data holding circuit 810, from one bit position to the next, and sets a bit-based comparison flag 220 for example to a high level, when the data has been switched from the last cycle.    2. The majority decision circuit-data inversion flag generating circuit 310 counts the number of the high-level comparison flag 220 and, when the data 110 has been switched at N/2 or more bit positions, an inversion flag 410 is set for example to a high level.    3. As long as the inversion flag 410 is set, the data inverting circuit 510 inverts the data 110 on the data bus to output the resulting data as output data 500.    4. The previous data holding circuit 810 holds actually output data 500.    5. During a burst read operation, the processing from 1 to 4 is repeated.
Meanwhile, the previous data holding circuit 810 is provided with a reset signal 830 for setting the previous data signal to the initial state such as a low level before start of read operation of the memory cell array.
By the above-described operation of the data inversion circuit, shown in FIG. 8, the number of inverted bits in the output data 500 is suppressed to N/2 bits or less, thereby to reduce the switching noise produced by an output circuit and to reduce the power dissipation.
There is a known a circuit configuration described in a reference 1 which compares (Ex-ORing) read data of a given cycle and read data of the directly previous cycle, a number of times equal to the number of bits, in an LSI chip, executes a majority decision of the number of changes in the value, and outputs an inverted (e.g. low-level) flag signal when the number of changes (the number of bits inverted from the read data of the last cycle) represents a majority, such as not less than N/2, while outputting reverse-phase data as output data. The result is that, if the number of the inverted bits is not less than one-half, reverse phase data may be output, whereby the number of bits inverted in the data output from the output buffer may be reduced to not larger than one-half. There is also a function of simultaneously outputting a flag signal, indicating the fact of inversion, to an external device, to advise the external device as to whether or not the output data has been inverted. Consequently, this technique belongs to the conventional circuit having a data inversion function as shown in FIG. 8.
Circuits having described in following references 2 and 3 which substantially have the object, effect and means for attaining the object in common with that of the reference 1, may be comprehended as belonging to the conventional technique shown in FIG. 8.
[reference 1]
JP Patent Kokai Publication JP-A-7-20973 (pages 2 to 4, FIG.)
[reference 2]
JP Patent Kokai Publication JP-A-8-101813 (page 3, FIG. 2)
[reference 3]
JP Patent Kokai Publication JP-A-10-198475 (page 4, FIG. 1)